Un proyecto de educación que nunca tendrá Bolivia, a menos que el chavismo lo financie:
Monday, July 7, 2008
One Laptop Per Child
Un proyecto de educación que nunca tendrá Bolivia, a menos que el chavismo lo financie:
Friday, July 4, 2008
x86-64 or AMD64
x86-64 is a 64-bit superset of the x86 instruction set architecture. Because the x86-64 instruction set is a superset of the x86 instruction set, all instructions in the x86 instruction set can be executed by central processing units (CPUs) that implement the x86-64 instruction set; therefore those CPUs can natively run programs that run on x86 processors from Intel, Advanced Micro Devices (AMD), and other vendors.
x86-64 was designed by AMD, who have since renamed it AMD64. It has been cloned by Intel under the name Intel 64 (formerly known as EM64T among other names).[1] This leads to the common use of the names x86-64 or x64 as more vendor-neutral terms to collectively refer to the two nearly identical implementations.
x86-64 should not be confused with the Intel Itanium architecture, also known as IA-64, which is not compatible on the native instruction set level with the x86 or x86-64 architecture.
Linux x86-64
- See also: List of 64-bit Linux distributions
Linux also provides backward compatibility for running 32-bit executables. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. Several Linux distributions currently ship with x86-64-native kernels and userlands. Some, such as SUSE, Mandriva and Debian GNU/Linux package both 32-bit and 64-bit systems on a single DVD-ROM image to allow automatic selection of the best software during installation.
Other distributions, such as Ubuntu, are available in a version compiled for 32-bit and one compiled for x86-64 architecture.
64-bit Linux allows up to 247 bytes (128 TiB) of address space for individual processes, and can address approximately 246 (64 TiB) of physical memory, subject to processor and system limitations.
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Pentium 4 types (Codes)
Pentium 4 Processors, Designations, and Characteristics
| Public Desig nation | Core (Intel Code name) | CPU Frequency | Frontside Bus Frequency / Theoretical Bandwidth | Cache | Additional Features |
| (ori- ginal rel. revi- sion) | Willamette | 1.3 GHz - 2.0 GHz | 100 MHz / 3.2 GB/s | 8 KiB L1 data + 12 KiB L1 instruction / 256 KiB L2 | N/A |
| P4A | Northwood | 1.6 GHz - 3.0 GHz | 100 MHz / 3.2 GB/s | 8 KiB L1 data + 12 KiB L1 instruction / 512 KiB L2 | Improved branch prediction and other microcodes tweaks; these are carried over into subsequent revisions |
| P4B | Northwood | 2.0 GHz - 3.06 GHz | 133 MHz / 4.2 GB/s | 8 KiB L1 data + 12 KiB L1 instruction / 512 KiB L2 | No change from P4A, except for Hyper threading in the 3.06 GHz model |
| P4C | Northwood | 2.4 GHz - 3.4+ GHz | 200 MHz / 6.4 GB/s | 8 KiB L1 data + 12 KiB L1 instruction / 512 KiB L2 | Hypert hreading |
| P4E | Prescott | 2.8 GHz - 3.8+ GHz | 200 MHz / 6.4 GB/s | 16 KiB L1 data + 12 KiB L1 instruction / 1 MiB L2 | Hypert hreading, longer pipeline, SSE3 instruc tions |
| P4A* | Prescott | 2.4 and 2.8 GHz | 133 MHz / 4.2 GB/s | 16 KiB L1 data + 12 KiB L1 instruction / 1 MiB L2 | No Hyper threading, longer pipeline, SSE3 instructions |
| Extre me Edition | Gallatin | 3.2 GHz - 3.4 GHz | 200 MHz / 6.4 GB/s | 8 KiB L1 data + 12 KiB L1 instruction / 512 KiB L2 / 2 MiB L3 | Hypert hreading, addition of on-die L3 cache |
| P4F | Prescott | 3.2 GHz - 3.8 GHz | 200 MHz / 6.4 GB/s | 16 KiB L1 data + 12 KiB L1 instruction / 1 MiB L2 | Support of EM64T and eXecute Disable bit (equivalent of AMD's No eXecute bit) |
| 6xx series | Prescott 2MB** | 2.8 GHz - 3.6 GHz | 200 MHz / 6.4 GB/s | 16 KiB L1 data + 12 KiB L1 instruction Per Core / Shared 2 MiB L2 | Larger L2 cache, support of EM64T and SpeedStep |
| Pentium D# | Smithfield | 2.8 GHz - 3.2 GHz | 200 MHz / 6.4 GB/s | 16 KiB L1 data + 12 KiB L1 instruction Per Core / Shared 2 MiB L2 | Support of EM64T and eXecute Disable bit (equivalent of AMD's No eXecute bit) Dual Core Processor |
| Notes: Pentium 4 processors use a frontside bus that transfers data four times per cycle * - in the case of the budget Prescott processor line, Intel duplicated the "P4A" designation which retailers are supposed to use to identify the processor to buyers; no reason was given for this decision ** - the official core name for the 600-series, though the core is sometimes called by its Xeon equivalent, Irwindale in order to distinguish between it and the initial Prescott. # - the Pentium D consists of 2 Prescott cores on a single die. | |||||
Wednesday, July 2, 2008
x86 virtualization
Hardware support
Intel and AMD have independently developed virtualization extensions to the x86 architecture. They are not directly compatible with each other, but serve largely the same functions. Either will allow a virtual machine hypervisor to run an unmodified guest operating system without incurring significant emulation performance penalties.
AMD virtualization (AMD-V)
AMD's virtualization extensions to the 64-bit x86 architecture is named AMD Virtualization, abbreviated AMD-V. It is still referred to as "Pacifica", the AMD internal project code name.AMD-V is present in AMD Athlon 64 with family "F" and "G" on socket AM2 not 939, Athlon 64 X2 with family "F" and "G", Turion 64 X2, Opteron 2nd generation[1] and 3rd generation[2], Phenom, and all newer processors.
AMD has published a specification for a technology named IO Memory Management Unit (IOMMU) to AMD-V. This provides a way of configuring interrupt delivery to individual virtual machines and an IO memory translation unit for preventing a virtual machine from using DMA to break isolation. The IOMMU also plays an important role in advanced operating systems (absent virtualization) and the AMD Torrenza architecture.
Intel VT (IVT)Intel's virtualization extension for 32-bit and 64-bit x86 architecture is named IVT (short for Intel Virtualization Technology), and is sometimes referred to by the development code name "Vanderpool". The 32-bit or IA-32 IVT extensions are referred to as VT-x.[3] Intel has also published specifications for IVT for the IA-64 (Itanium) processors which are referred to as VT-i;[3] formerly the IA-64 virtualization was code-named "Silvervale".Intel will add EPT (Extended Page Tables) to the VT-x architecture. See link: http://www.intel.com/technology/itj/2006/v10i3/1-hardware/8-virtualization-future.htm
Intel VT was officially launched at the Intel Developer Forum Spring 2005. It is available on certain Pentium 4 6x1 and 6x2 models,[4] Pentium D 9x0[5], Xeon 3xxx/5xxx/7xxx, Core Duo[6] (excluding the T2300E and T2x50 models) and Core 2 Duo[7] processors (excluding the T52x0, T5300, T54x0, T5500 with stepping "B2", E2xx0, E4x00, E7200 and E8190 models). On some implementations, IVT support may be switched off in the Firmware. This can be determined by checking if the VMX flag is enabled by the Feature Control MSR.
Documentation on the Intel website has stated that VT requires not only support from the processor, but also support from the chipset, BIOS, hypervisor, Guest OS (software drivers for e.g. NICs), NICs themselves (see Intel 10 Gb Server NICs with virtualization support) and sometimes software [8][9]Intel plans to add a technology named Virtualization for Directed I/O (VT-d) to VT. This provides a way of configuring interrupt delivery to individual virtual machines and an IOMMU for preventing a virtual machine from using DMA to break isolation.
Intel also developed a technology named Intel Virtualization Technology for Connectivity ("VT-c") to VT. Intel Virtual Machine Device queues ("VMDq") is a component of VT-c. See this linkAnd then there is Intel Input/Output Acceleration Technology ("Intel I/OAT"). Intel® QuickData Technology is a component of Intel I/OAT.
Pentium 4 for VT
Pentium D supporting VT
"Presler" (dual core, 65 nm)
- All models support: MMX, SSE, SSE2, SSE3, Enhanced Intel SpeedStep Technology (EIST), Intel 64 (an x86-64 implementation), XD bit (an NX bit implementation)
- Virtualization Technology supported by: models 9x0
- Steppings: B1, C1 & D0
| Model Number | sSpec Number | Freq | L2-Cache | Front Side Bus | Mult | Voltage | TDP | Release Date | Part Number | ||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Pentium D 915 | SL9DA (C1) SL9KB (D0) | 2,8 GHz | 2 × 2048 KiB | 800 MT/s | 14x | 1.2/1.337 V | 95 W | July 23, 2006 | HH80553 PG0724MN | ||
| Pentium D 920 | SL94S (B1) SL95Y (C1) | 2,8 GHz | 2 × 2048 KiB | 800 MT/s | 14x | 1.2/1.337 V | 95 W | January 16, 2006 | HH80553 PG0724M | ||
| Pentium D 925 | SL9D9 (C1) SL9KA (D0) | 3,0 GHz | 2 × 2048 KiB | 800 MT/s | 15x | 1.2/1.337 V | 95 W | October 2006 | HH80553 PG0804MN | ||
| Pentium D 930 | SL94R (B1) SL95X (C1) | 3,0 GHz | 2 × 2048 KiB | 800 MT/s | 15x | 1.2/1.337 V | 95 W | January 16, 2006 | HH80553 PG0804M | ||
| Pentium D 935 | SL9QR (D0) | 3,2 GHz | 2 × 2048 KiB | 800 MT/s | 16x | 1.2/1.337 V | 95 W | January 2007 | HH80553 PG0884MN | ||
| Pentium D 940 | SL94Q (B1) | 3,2 GHz | 2 × 2048 KiB | 800 MT/s | 16x | 1.2/1.337 V | 130 W | January 16, 2006 | HH80553 PG0824M | ||
| SL95W (C1) | 95 W | ||||||||||
| Pentium D 945 | SL9QB (C1) SL9QQ (D0) | 3,4 GHz | 2 × 2048 KiB | 800 MT/s | 17x | 1.2/1.337 V | 95 W | July 23, 2006 | HH80553 PG0964MN | ||
| Pentium D 950 | SL94P (B1) | 3,4 GHz | 2 × 2048 KiB | 800 MT/s | 17x | 1.2/1.337 V | 130 W | January 16, 2006 | HH80553 PG0964M | ||
| SL95V (C1) | 95 W | ||||||||||
| SL9K8 (D0) | |||||||||||
| Pentium D 960 | SL9AP (C1) | 3,6 GHz | 2 × 2048 KiB | 800 MT/s | 18x | 1.2/1.337 V | 130 W | May 2, 2006 | HH80553 PG1044M | ||
| SL9K7 (D0) | 95 W |
"Presler" (dual core, 65 nm)
- All models support: MMX, SSE, SSE2, SSE3, Hyper-Threading, Enhanced Intel SpeedStep Technology (EIST), Intel 64 (an x86-64 implementation), XD bit (an NX bit implementation), Virtualization Technology
- Steppings: B1, C1
| Model Number | sSpec Number | Frequency | L2-Cache | Front Side Bus | Mult | Uc,Uio | TDP | Release Date | Part Number | ||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Pentium Extreme Edition 955 | SL94N (B1) | 3466 MHz | 2 × 2048 KiB | 1066 MT/s | 13x | 1.2/1.337 V | 130 W | Jan 16, 2006 | HH80553 PH0994M | ||
| Pentium Extreme Edition 965 | SL9AN (C1) | 3733 MHz | 2 × 2048 KiB | 1066 MT/s | 14x | 1.2/1.337 V | 130 W | Mar 22, 2006 | HH80553 PH1094M |
Pentium Extreme Edition
Monday, June 16, 2008
Saturday, June 14, 2008
32 or 64 bit Processor? Dual Core?
Example:
$ uname -r
2.6.18-8.el5
How many physical processors are there?
$ grep 'physical id' /proc/cpuinfo | sort | uniq | wc -l2
How many virtual processors are there?
$ grep ^processor /proc/cpuinfo | wc -l4
Are the processors dual-core (or multi-core)?
$ grep 'cpu cores' /proc/cpuinfocpu cores : 2
cpu cores : 2
cpu cores : 2
cpu cores : 2
"2" indicates the two physical processors are dual-core, resulting in 4 virtual processors.
If "1" was returned, the two physical processors are single-core. If
the processors are single-core, and the number of virtual processors is
greater than the number of physical processors, the CPUs are using
hyper-threading. Hyper-threading is supported if ht is present in the CPU flags and you are using an SMP kernel.
Are the processors 64-bit?
A 64-bit processor will have lm ("long mode") in the flags section of cpuinfo. A 32-bit processor will not.e.g.,
flags
: fpu vme de pse tsc msr pae mce cx8 apic mtrr pge mca cmov pat pse36
clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt lm 3dnowext 3dnow pni cx16 lahf_lm cmp_legacy svm cr8legacy ts fid vid ttp tm stc
What do the CPU flags mean?
The CPU flags are briefly described in the kernel header file cpufeature.h.Back to brandonhutchinson.com.
Thursday, May 1, 2008
WiTricity
Wireles elecTricity