AMD 700 chipsets

The AMD 700 chipset series (also called as AMD 7-Series Chipsets) is a set of chipsets designed by ATI for AMD Phenom processors to be sold under the AMD brand. Several members were launched in the end of 2007 and the first half of 2008, others launched throughout the rest of 2008.

• 1 Development history
• 2 Line-up
  • 2.1 790FX
  • 2.2 790X
  • 2.3 790GX
  • 2.4 785G
    • Codenamed RS880
    • Single AMD processor configuration
    • One physical PCIe 2.0 x16 slot, one PCIe 2.0 x4 slot and two PCIe 2.0 x1 slots, the chipset provides a total of 22 PCIe 2.0 lanes and 4 PCIe 1.1 for A-Link Express II solely in the Northbridge
    • Integrated graphics: Radeon HD 4200
      • ATI Hybrid Graphics and PowerXpress
      • Side-port memory as local frame buffer, supporting DDR2 and GDDR3 chips
      • UVD 2
      • ATI Stream capabilities
    • No 7.1-channel LPCM support^[19]
    • HyperTransport 3.0 and PCI Express 2.0
    • AMD OverDrive
    • Energy efficient Northbridge design
      • 55 nm CMOS fabrication process by TSMC
    • Mainstream hybrid graphics (DirectX 10.1 IGP) segment
    
    
    
  • 2.5 785E
  • 2.6 780G/780V
  • 2.7 780E
  • 2.8 770
  • 2.9 760G
  • 2.10 740G
  • 2.11 740
  • 2.12 Southbridges
• 3 Key features
  • 3.1 Multi-graphics
  • 3.2 AMD OverDrive
  • 3.3 AutoXpress
  • 3.4 Advanced Clock Calibration
  • 3.5 Energy efficiency
  • 3.6 ATI Hybrid Graphics
  • 3.7 I/O acceleration technologies
  • 3.8 Integrated graphics
  • 3.9 "Remote IT"
• 4 Reception
• 5 Northbridge issues(760G, M770, 780x, M780x, 790GX)
• 6 Southbridge issues(SB7x0)
• 7 See also
• 8 References
• 9 External links

Advanced Clock Calibration

Advanced clock calibration (ACC) is a feature originally available for Phenom families of processors, particularly for Black Edition ones, to increase the overclocking potential of the CPU. ACC is supported by the SB710 and the SB750 southbridges, and available through BIOS settings on some motherboards and AMD OverDrive utility.^[43]

It was later discovered that this functionality has the possibility of unlocking the supposedly disabled cores of some Phenom II X2/X3 processors. In normal cases, it is not possible to use or unlock any of those hidden cores because originally those cores were disabled: a technique called "chip harvesting" or "feature binning" used by AMD to sell parts with one or two defective cores which will cause system instability if not disabled.

The following are available through the Advanced Clock Calibration feature:

1. Auto or manual settings
2. Allow separate settings for each of the CPU cores
3. Allowed range: -12% to +12%
4. Possibility of unlocking AMD Phenom II X2/X3, AMD Athlon II X2/X3 and AMD Sempron locked cores / cache. (with BIOS support)

The principle of ACC is not publicly discussed by AMD but some third-party vendors, including ASUS (Core Unlocker)^[44] and Biostar (BIO-unlocKING)^[45] have had it for some time. Gigabyte has added this feature, called CPU Core Control, to many NB785/SB710 boards via BIOS update^[46], and will be including this feature (now called Auto Unlock) in all of their 800 Series boards with the SB850 chip^[47]. On many of the boards, the feature is dependent on BIOS version. 

While NVIDIA also has a similar technology for its nForce 780a motherboards, called NVCC (NVIDIA Clock Calibration) with very similar functionality.

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Northbridge issues(760G, M770, 780x, M780x, 790GX)

• All platforms:
  • Low speed instability with HyperTransport version 3 capable processors. HT3 speeds 1.2 GHz up to 1.6 GHz should not be used, only 1.8 up to 2.2 GHz speeds are safe to be used. HT3 processors operating at 1.6 GHz(Phenom X3 8250e, Phenom X4 9100e and Phenom X4 9150e) will suffer from high retry count on the HyperTransport link which may result in hangs on revision A12 northbridges.
• Windows platform:
  • Microsoft KB959345^[60]

Southbridge issues(SB7x0) Most OSes require patches in order to work reliably.

• Windows platform:
  • Microsoft KB982091^[61]
  • Microsoft KB956871^[62]
  • Microsoft KB953689^[63]
• Linux platform:
  • HPET operation with MSI causes LPC DMA corruption on devices using LPC DMA (floppy, parallel port, serial port in FIR mode) because MSI requests are misinterpreted as DMA cycles by the broken LPC controller^[64]
  • USB freeze when multiple devices are connected through hub (related to AMD Product Advisory PA_SB700AK1)^[65]
  • Erratic behaviour of the HPET when Spread Spectrum is enabled (related to AMD Product Advisory PA_SB700AG2)^[66]
  • Disabling legacy interrupts for SATA disables MSI too^[67]
  • SATA soft reset fails when PMP is enabled and attached devices will not be detected
  • SATA internal errors are ignored because the controller will set Serial ATA port Error when it should not

See also

• AMD 800 chipset series
• AMD 900 chipset series
• nForce 700
• Advanced Micro Devices
• ATI Technologies
• Comparison of AMD Chipsets
• Comparison of ATI graphics processing units

Chipset technologiies

Chipset

A typical north/southbridge layout

The northbridge has historically been one of the two chips in the core logic chipset on aPC motherboard, the other being the southbridge. Increasingly these functions have migrated to the CPU chip itself, beginning with memory and graphics controllers. In Intel "Sandy Bridge" CPU designs introduced in 2011, all of the functions of the northbridge reside on the chip itself.^[1] When the separate northbridge is employed in older Intel systems it is named memory controller hub (MCH) or integrated memory controller (IMCH) if equipped with an integrated VGA.

Separating the chipset into the northbridge and southbridge is common, although in some instances the northbridge and southbridge functions were combined onto one die when design complexity and fabrication processes permitted it.

Contents   1 Overview

The northbridge typically handles communications among the CPU, in some cases RAM, and PCI Express (or AGP) video cards, and the southbridge.^[2][3]Some northbridges also contain integrated video controllers, also known as aGraphics and Memory Controller Hub (GMCH) in Intel systems. Because different processors and RAM require different signaling, a northbridge will typically work with only one or two classes of CPUs and generally only one type of RAM.

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The southbridge is one of the two chips in the core logic chipset on apersonal computer(PC) motherboard, the other being the northbridge. The southbridge typically implements the "slower" capabilities of the motherboard in a northbridge/southbridge chipset computer architecture. In Intel chipset systems the southbridge is named Input/Output Controller Hub (ICH).

The southbridge can usually be distinguished from the northbridge by not being directly connected to the CPU. Rather, the northbridge ties the southbridge to the CPU. Through the use of controller integrated channel circuitry, the northbridge can directly link signals from the I/O units to the CPU for data control and access.

Functionality

Diagram of a modern motherboard, which supports many on-board peripheral functions as well as several expansion slots.

The functionality found in a contemporary southbridge includes:

• PCI bus. The PCI bus support includes the traditional PCI specification, but may also include support forPCI-X and PCI Express.
• ISA bus or LPC Bridge. Though the ISA support is rarely utilized, it has interestingly managed to remain an integrated part of the modern southbridge. The LPC Bridge provides a data and control path to theSuper I/O (the normal attachment for the keyboard, mouse, parallel port, serial port,IR port, and floppy controller) and FWH (firmware hub which provides access to BIOS flash storage).
• SPI bus. The SPI bus is a simple serial bus mostly used for firmware (e.g.,BIOS) flash storage access.
• SMBus. The SMBus is used to communicate with other devices on the motherboard (e.g., system temperature sensors, fan controllers).
• DMA controller. The DMA controller allows ISA or LPC devices direct access to main memory without needing help from the CPU.
• Interrupt controllers such as 8259A and/or I/O APIC. The interrupt controller provides a mechanism for attached devices to get attention from the CPU.
• Mass storage controllers such as PATA and/or SATA. This typically allows direct attachment of system hard drives.
• Real-time clock. The real time clock provides a persistent time account.
• Power management (APM and ACPI). The APM or ACPI functions provide methods and signaling to allow the computer to sleep or shut down to save power.
• Nonvolatile BIOS memory. The system CMOS, assisted by battery supplemental power, creates a limited non-volatile storage area for system configuration data.
• AC'97 or Intel High Definition Audio sound interface.
• Out-of-band management controller such as a BMC or HECI.

Optionally, a southbridge also includes support for Ethernet, RAID, USB, audio codec, and FireWire. Rarely, a southbridge may also include support for the keyboard, mouse, and serial ports, but normally these devices are attached through another device referred to as the Super I/O.

FSB, Memory Bus, DDR, Dual Channel

Source
My FSB is 200 MHz (my motherboard support 800 MHz)...
And my bus speed is 800 MHz!
What is the difference here?
Why only 200 MHz when I check it?

Specs for the CPU:
Intel Pentium4 2.6 GHz / Hyper Threading
Core: Northwood
Frequency: 2.6GHz
FSB: 800MHz
Cache: L1 12KB+8KB; L2 512KB

Specs for the Mobo:
Model: 865PE Neo2-LS
Supported CPU: Socket 478 Pentium 4 Processors(Hyper-Threading)
Chipset: Intel 865PE + ICH5
FSB: 800/533/400MHz
RAM: 4x DIMM support Dual Channel DDR 400/333/266 Max 4GB

Answer:
You are using DDR PC 3200 memory, also called 400 Mhz DDR
The memory bus [from memory to the MCH chip] runs at 200 MHz.
HOWEVER DDR (Double Data Rate) makes TWO reads|writes per clock cycle, once on the leading edge and once on the trailing edge, thus 2 X 200 = 400.

Then Dual Channel does the rest.
The mobo/chipset actually has TWO memory busses from the memory to the MCH chip.
The MCH stages these two memory busses to the CPU such that the CPU is getting FOUR read/writes per clock cycle.
Thus 2 X 400 = 800.

Of course you must have two memory sticks of same size et al, one in the even slot and one in the odd slot so that both memory busses are being fed from memory.

MCH [formerly Northbridge] is Memory Controller Hub
ICH [formerly Southbridge] is I/O Controller Hub.
Substantially improved from original NorthBridge and SouthBridge.
The interface between the ICH and MCH is far faster than what existed in the NB/SB interface. Those chipsets were designed to remove as many readblocks as possible for all types of data transfers.
BTW the AMD 64 bit CPU's have the MCH on the CPU chip.
The lower priced AMD MCH does NOT handle Dual Channel, only the higher priced version has a builtin MCH that handles Dual Channel.

PAT

Source (excerpts)

PAT stands for Performance Acceleration Technology used in certain Intel chipsets as 875P MCH chip.
What Intel is doing, in fact, is "binning" its chips, just like it does its processors.
In all likelihood, the 875P silicon will come from the same wafers and essentially be the same chips as Intel's upcoming Springdale chipset, but Springdale will be a cheaper, higher-volume product. (Springdale chipsets will differ from the 875P only in that they won't include PAT or support for ECC memory types.)
The 875P will cost a little more, and will be aimed at workstation users and enthusiasts.
Intel probably plans to pick the very fastest Canterwood/Springdale MCH (north bridge) chips and test them to verify they're capable of running with PAT enabled.
The best of those chips will be sold as 875P MCH chips.
With PAT enabled, the 875P memory controller will perform some internal memory handling tasks faster, yielding a one-clock improvement in the time for a CPU request to perform memory access and another one-clock improvement in the DRAM chip select process.

The total improvement is two clocks for each chip select (CS) process. CS happens at the beginning of a typical memory access, so cutting the CS process by two cycles could lead to real-world reductions in memory access latency.
Intel emphasizes that 875P chipsets are tested rigorously, at full operating speed, for their ability to run with PAT enabled, so Canterwood motherboards ought to be plenty stable under normal operating conditions. Intel is also quick to point out that PAT happens internally in the memory controller, while external memory interfaces run according to their specifications.

A block diagram of the 875P chipset — Source: Intel